1. Field of the Invention
This invention relates generally to frequency synthesizing circuits and system. More particularly, this invention relates to fractional-N frequency synthesizers, where an output frequency of the synthesizer is a non-integer multiple of a reference frequency. Even more particularly, this invention relates to fractional-N frequency synthesizers where the initial output frequency, frequency increment or step size, and a difference between channel frequencies are controlled by multiple input variables.
2. Description of Related Art
A frequency synthesizer, as is known in the art and described in xe2x80x9cFractional-N Synthesizersxe2x80x94White Paperxe2x80x9d, Staff, Conexant Systems, Inc., Newport Beach, Calif., February, 2001, is fundamentally a phased locked loop (PLL). A phase locked loop is a negative feedback oscillator that employs a phase frequency detector with a charge pump, a low pass filter, and a voltage controlled oscillator. The phase frequency detector receives a reference frequency and compares the phase of the output frequency to the phase of the input frequency and provides an error voltage indicating the difference in phase of the output frequency versus the reference frequency. The error voltage is passed through the low pass filter to eliminate any spurious transients in the error voltage. The filtered error voltage is applied to the voltage controlled oscillator. The error voltage changes the frequency of the voltage controlled oscillator until the phase and frequency of the output signal is equal to that of the reference input signal.
A phase locked loop becomes a frequency synthesizer when a frequency divider is applied between the fed back output frequency signal of the voltage controlled oscillator and the input of the phase frequency detector. The output frequency signal now becomes a multiple of the input frequency and that multiple is the modulus of the frequency divider. The frequency divider is in essence a state machine that is clocked by the output frequency signal of the voltage controlled oscillator. The output of the state machine changes state, whenever the output frequency signal has occurred the number of times of the modulus.
The frequency synthesizer becomes programmable when the modulus of the frequency divider is a digital number placed in a register of the frequency divider. The output frequency of the frequency synthesizer is an integer multiple of the reference frequency, even with a programmable modulus. Thus, the incremental frequency change for the output frequency signal is the magnitude of the frequency of the reference input.
In order to achieve an output frequency of the synthesizer that is not only an integer multiple of the reference frequency, but is a fractional multiple of the reference frequency, a fractional-N synthesizer was developed. Refer now to FIG. 1 for a discussion of the structure and operation of a dual modulus fractional-N frequency synthesizer. As discussed above, the frequency synthesizer is essentially a phase locked loop having a phase frequency detector 10 into which the reference input signal (Fr) 5 is applied. The phase frequency detector 10 incorporates a charge pump which provides an output voltage that is applied to the low pass filter 15. The low pass filter 15 removes any spurious transients from the output voltage and applied the filter voltage level to the voltage controlled oscillator 20. The filtered voltage level determines the frequency of the output signal (Fo) 25. The output signal (Fo) 25 is the input to the dual modulus frequency divider 30. The dual modulus frequency divider 30 divides the output signal (Fo) 25 by the factor N or N+1 dependent on the mode signal 40. The divided output signal (Fd) 35 is applied to the phase frequency detector 10 for comparison to the reference input signal (Fr) 5 to create the voltage level to adjust the frequency of the voltage controlled oscillator 20.
The modulus controller 45 generates the mode signal 40 as a function of the density data input (K) 50. The density data input (K) 50 is generally repetitively added to itself until there is an overflow of the addition. The overflow is used to cause the mode signal 40 to change the modulus of the dual modulus frequency divider 30. The repetitively addition of the density data input (K) 50 causes the frequency of the output signal (Fo) 25 to be determined by the equation:
Fo=Nav*Fr
where:
Fo is the output signal 25.
Fr is the reference input signal 5.
Nav=N+K/2n
where:
N is the primary modulus of the dual modulus divider.
K is the density data input 50.
n is the number of bits in the density data input (K) 50.
The structure of the frequency synthesizer may be implemented in variations of the structure as described. In general the fundamental parameters are according to the following equations:
1. The step size of the increment of the frequency synthesizer is:
Fstep=Fr*1/2n
here:
Fstep is the step size of the increments of that the frequency synthesizer may be adjusted
Fr is the reference input signal 5.
n is the number of bits in the density data input (K) 50.
2. The minimum frequency of the output signal (Fo) 25 is:
Fo min=N*Fr
where:
Fomin is the minimum frequency of the output signal (Fo) 25.
Fr is the reference input signal 5.
N is the primary modulus of the dual modulus divider 30.
3. The maximum frequency of the output signal (Fo) 25 is:
Fo max=(N+1)*Fr
where:
Fomax is the maximum frequency of the output signal (Fo) 25.
Fr is the reference input signal 5.
N+1 is the secondary modulus of the dual modulus divider 30.
4. The reference input signal (Fr) 5 is the difference between the maximum frequency and the minimum frequency of the output signal (Fo) 25 or:
Fr=Fo maxxe2x88x92Fo min.
xe2x80x9cA Low Phase Noise C-Band Frequency Synthesizer Using a New Fractional-N PLL with Programmable Fractionality,xe2x80x9d Nakagawa et al., IEEE Transactions on Microwave Theory and Techniques, Volume: 44, Issue: 2, pp. 344-346, February 1996 describes a fractional-N phase locked loop that has an arbitrary denominator of the fractional division ratio as well as an arbitrary numerator and an integer part. In this case, the resulting modulus of the dividing factor N is now an averaged factor Nav which is now found by the equation:
Nav=N+A/M
where:
N, A, and M are programmable factors of the frequency synthesizer.
U.S. Pat. No. 6,219,397 (Park) describes a Phase-Locked-Loop-based CMOS fractional-N frequency synthesizer. The frequency synthesizer has an on-chip LC Voltage Controlled Oscillator. A higher-order discrete sigma-delta modulator is used in the fractional-N frequency synthesizer resulting in a strong attention at low frequencies for quantization noise. The synthesizer employs a noise shaping method to suppress fractional spurs using the high-order sigma-delta modulator.
U.S. Pat. No. 4,758,802 (Jackson) teaches a Fractional N synthesizer. The fractional N synthesizer includes a voltage controlled oscillator which produces an output signal that is transferred to a phase detector via a variable divider to provide a control signal for the voltage controlled oscillator in the presence of a phase difference between a reference signal from a reference source and the signal from the variable divider. The synthesizer has two accumulators, the arrangement of the accumulators being such that an output signal that cancels the interpolation sidebands of the first accumulator caused by quantization errors in the first accumulator. The division ratio of the variable divider is set depending upon the output signal.
U.S. Pat. No. 5,224,132 (Goldberg) provides a programmable fractional-N frequency synthesizer The frequency synthesizer has a fractional divider using a counter to provide a fraction for the divider. The divider is used to divide the VCO output signal by N or N+1 as selected. A divider control circuit controls the divider to divide by the appropriate divisor to obtain the selected output frequency. The fractional divider circuit counts divider control signals which represent a first division period. The fractional divider circuit establishes a second period of multiple first periods and at the terminal count of each second period, the fractional divider circuits provides a selected number of fractional control signals to the divider control to cause division by a different number, such as N+1. The fractional divider includes a first counter programmed to count first periods and issue its terminal count upon receiving the programmed count of first periods The fractional divider also comprises a second counter to provide the selected number of fractional control signals upon receipt of the terminal count of the first counter. The first and second counters thus operate as a fraction for instance F/K results in a fractional reference frequency.
U.S. Pat. No. 5,714,896 (Nakagawa, et al.) describes a fractional-N frequency divider system that generates an output signal having frequency of an input signal divided by a desired frequency division ratio (N+A/M) in which N is an integer and A/M is a fraction, Axe2x89xa6M. The frequency divider includes a programmable frequency divider receiving input frequency and providing divided frequency in which the division ratio (N, N+1) is an integer and is externally supplied. A selector supplies one of the externally supplied integers (N, N+1) to the divider according to a selection signal and a fractional part set having a first counter initialized to count M, a second counter initialized to count A, and a logic circuit for supplying the selection signal according to the counters. The counters are decremented by an output of the divider and reach zero when they receive M and A number of pulses, respectively The second counter stops counting operation when it reaches zero. The logic circuit makes the selector select an integer N in a condition when content of the first counter is not zero and content of the second counter is zero, and N+1 in other conditions, so that the division ratio in the divider is N+1 for A number of output pulses of the divider among M number of output pulses, and is N for M-A number of the output pulses
U.S. Pat. No. 5,777,521 (Gillig, et al.) describes a parallel accumulator fractional-n frequency synthesizer. The frequency synthesizer includes a synthesizer loop with a fractional-N divider, and including a divider control circuit and a combining circuit. The divider control circuit provides a variable divide value to the divider. The carry values of two accumulators having differing accumulator lengths are applied in parallel to the combining circuit. Each of the accumulators provides a portion of a desired fractional divide value. The combining circuit also adds an integer divide value to the fractional divide value.
U.S. Pat. No. 5,124,670 (Lawton) teaches a frequency synthesizer with fractional division. The fractional-N synthesizer includes a phase locked loop that has a voltage controlled oscillator providing a loop output signal. The output signal is coupled via an N variable divider to a first input of a phase or frequency detector. A reference frequency source coupled to a second input of the phase or frequency detector. The detector provides an output a control signal that is dependent upon a comparison between the signals applied to the first and second inputs, for application to a control input of the voltage controlled oscillator. The synthesizer includes a circuit for setting the division ratio (N) of the variable divider in response to a frequency data word. The circuit includes an interpolator for periodically varying at least the LSB of the frequency data word. The interpolator has an input for receiving the LSB, a combiner for comparing the LSB with a feedback signal, a quantizer circuit, and a filter circuit. The quantizer circuit and the filter circuit provide a predetermined delay or integration function. The quantizer circuit and filter circuit are coupled to the combiner for providing said feedback signal and a ratio setting signal to the variable divider.
xe2x80x9cApplication Note for SA8025 Fractional-N synthesizer for 2 GHz band applications,xe2x80x9d AN1891, Djen, Philips Semiconductors, Aug. 20, 1997, describes the SA8025, which is a 3V, 1.8 GHz, SSOP 20-pin packaged fractional-N phase locked-loop (PLL) frequency synthesizer.
xe2x80x9cA 5 Ghz, 32 Mw CMOS Frequency Synthesizer With an Injection Locked Frequency Divider,xe2x80x9d Rategh, Digest of Technical Papers 1999 Symposium on VLSI Circuits, Kyoto, Japan, 1999, IEEE, pp. 113-116, ISBN: 4-930813-95-6, describes a fully integrated 5 GHz phase locked loopxe2x80x94(PLL-) based frequency synthesizer. A voltage-controlled differential injection-locked frequency divider (VCDILFD) is used as the first frequency divider in the PLL feedback loop to reduce power consumption and eliminate the need for an off-chip frequency divider.
An object of this invention is to provide a fractional-N frequency synthesizer having a modulus controller with multiple inputs that control an initial output frequency of the frequency synthesizer, an increment of variation of tuning of the frequency synthesizer, and a difference between two adjacent output frequency settings.
To accomplish at least this object, a fractional frequency synthesizer includes a multiple modulus frequency divider connected to receive the output frequency of a voltage controlled oscillator and dependant upon a modulus factor select one of a plurality of divisors for the output frequency to generate a divided output signal. The divided output signal is phased compared to a reference frequency signal to create the control voltage for the voltage controlled oscillator.
A modulus controller is in communication with the multiple modulus frequency divider to control the modulus factor for the multiple modulus frequency divider. The modulus controller has a first factor input, a second factor input and a gain factor input to respectively receive a first digital data word, a second digital data word and a gain factor digital data word. The first digital data word has a first number of bits and the second digital data word has a second number of bits. The gain factor digital data word is an integer multiplier for the first digital data word.
The modulus controller has a modulus selection circuit in communication with the first factor input, the second factor input, and the gain factor input. The modulus selection circuit provides a modulus control signal to the modulus divider to select the modulus factor of the modulus divider as a function of a sum of the second digital data word and a product of the first digital data word and the gain factor digital data word. The function of the sum of the second digital data word and the product of the first digital data word and the gain factor digital data word is an overflow from a continuous summation of the second digital data word and a product of the first digital data word and the gain factor digital data word repetitively with itself.
The data values of the first digital data word, the second data word, and the gain factor data word control an initial output frequency of the frequency synthesizer, an increment of variation of tuning of the frequency synthesizer, and a difference between two adjacent output frequency settings. There are primarily two ways of controlling the synthesizer behaviour. In the first approach, the increment of variation or step size of the output frequency is determined by the equation
Finc=(1/2n)xc2x7Fr
where:
Finc is the increment of variation of tuning, and
Fr is a reference frequency for the frequency synthesizer.
n is the number of bits representing the second data word.
The initial output frequency is determined by the equation:
Finit=Fr*Ad/2m
where:
Finit is the initial output frequency.
Fr is a reference frequency for the frequency synthesizer.
d is the first digital data word.
A is the gain factor digital data word, and
m is the number of bits representing the first data word.
In a second approach of the frequency synthesizer, the output frequency is adjusted by varying the gain factor digital data word. The increment of variation is determined by the equation
Finc=Fr*d/2m
where:
Finc is the increment of variation of tuning.
d is the first digital data word, and
m is the number of bits representing the first data word.
The initial output frequency is determined by the equation:
Finit=Fr*f/2n
where:
Finit is the initial output frequency.
Fr is a reference frequency for the frequency synthesizer.
f is the second digital data word, and
n is the number of bits representing the second data word.
The modulus selection circuit includes a gain factor counter to provide an enable signal indicating the number of counts of the reference clock equal to the gain factor data word. A first adder to repetitively add the first digital data word until the enable signal is active indicating the number of times the repetitive addition of the first digital data word has been completed. When the enable signal is active, a second adder adds the product of the gain factor digital data word and the first digital data word to the second digital data word. A third adder is in communication with the second adder to receive the sum of the second digital data word and a product of the first digital data word and the gain factor digital data word. The third adder output exclusive of the overflow signal is connected to one of the inputs of the third adder to repetitively add the sum of the second digital data word and a product of the first digital data word and the gain factor digital data word. The overflow signal is provided at an overflow output of the third adder, the overflow signal being the modulus control signal is applied to the multiple modulus frequency divider.